By Dimitris Gizopoulos
This is a brand new form of edited quantity within the Frontiers in digital checking out e-book sequence dedicated to contemporary advances in digital circuits checking out. The e-book is a finished elaboration on vital subject matters which catch significant examine and improvement efforts at the present time. "Hot" subject matters of present curiosity to check know-how group were chosen, and the authors are key participants within the corresponding topics.
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Additional resources for Advances in Electronic Testing: Challenges and Methodologies
In order to account for 6 A fault model is an abstraction of defect behavior. To be useful, a fault model must help in the development or evaluation of tests, or in yield improvement. Advances in Electronic Testing: Challenges and Methodologies 15 their behavior correctly, fault modeling will need to move from the discrete to the continuous domain. As the cost of developing CMOS manufacturing technology skyrockets, the number of independent efforts is declining. Bringing a new process technology to market already costs multiple billions of dollars, and this cost is rising with every process generation.
Multiple voltage tests will eliminate delay-independent Byzantine behavior. However, in addition to gate switching voltages, Byzantine behavior can be caused by gate switching times. Long settling times for bridging voltages lead to large skews on gate inputs, which in turn result in different switching times on gate outputs. If path slack is low enough that values are latched before switching is complete, Byzantine behavior can result, as shown in Figure 1-17. In theory, increasing clock speed could eliminate this problem, by latching data at the “latch 0” point rather than the “latch 1” point, but in practice running such tests is difficult.
If full circuit operating speed cannot be obtained, a reduced speed is often very effective (Maxwell et al found that 13 of 15 at-speed functional test fails would fail the same test at half speed ). 4 Very Low Voltage Another approach to finding delay problems that has found some success is very low voltage (VLV ) testing. The basic idea is that delay increases substantially as VDD lowers, and that this effect is more pronounced for faulty circuits. Thus, a test at low VDD can more easily detect defects difficult to detect at nominal VDD.
Advances in Electronic Testing: Challenges and Methodologies by Dimitris Gizopoulos